<parts>
    <!-- BANK 0 -->
    <regblock name="SFR0" start="0x0000" end="0x001F" >
        <register name="PORTA"   addr="0x05" 
                  bits="RA0,RA1,RA2,RA3,RA4,RA5,RA6,RA7"/>
                  
        <register name="PORTB"   addr="0x06" 
                  bits="RB0,RB1,RB2,RB3,RB4,RB5,RB6,RB7"/>

        <register name="PCLATH"  addr="0x0A" bits=""/>
        <register name="INTCON"  addr="0x0B" 
                  bits="RBIF,INTF,T0IF,RBIE,INTE,T0IE,PEIE,GIE"/>
                  
        <register name="PIR1"    addr="0x0C" mask="11110111"
                  bits="TMR1IF,TMR2IF,CCP1IF,0,TXIF,RCIF,CMIF,EEIF"/>
                  
        <register name="TMR1L"   addr="0x0E" bits=""/>
        <register name="TMR1H"   addr="0x0F" bits=""/>
        <register name="T1CON"   addr="0x10" bits="TMR1ON,TMR1CS,T1SYNC,T1OSCEN,T1CKPS0,T1CKPS1"/>
        <register name="TMR2"    addr="0x11" bits=""/>
        <register name="T2CON"   addr="0x12" bits="T2CKPS0,T2CKPS1,TMR2ON,TOUTPS0,TOUTPS1,TOUTPS2,TOUTPS3"/>
        <register name="CCPR1L"  addr="0x15" bits=""/>
        <register name="CCPR1H"  addr="0x16" bits=""/>
        <register name="CCP1CON" addr="0x17" mask="00111111"
                  bits="CCP1M0,CCP1M1,CCP1M2,CCP1M3,CCP1Y,CCP1X"/>
                  
        <register name="RCSTA"   addr="0x18" mask="11111000"
                  bits="RX9D,OERR,FERR,ADEN,CREN,SREN,RX9,SPEN" />
                  
        <register name="TXREG"   addr="0x19" bits=""/>
        <register name="RCREG"   addr="0x1A" mask="00000000" bits=""/>
        <register name="CMCON"   addr="0x1F" mask="00111111"
                  bits="CM0,CM1,CM2,CIS,C1INV,C2INV,C1OUT,C2OUT" />
    </regblock>
    <datablock name="GPR0" start="0x0020" end="0x006F"/>
    <datablock name="RAM0" start="0x0070" end="0x007F"/>
    
    <!-- BANK 1 -->
    <regblock name="SFR1" start="0x0080" end="0x009F">
        <mapped                  addr="0x80" mapto="0x00"/><!-- INDF -->
        <register name="OPTION" addr="0x81" reset="11111111"
                  bits="PS0,PS1,PS2,PSA,T0SE,T0CS,INTEDG,RBPU"/>
                  
        <mapped                  addr="0x82" mapto="0x02"/><!-- PCL -->
        <mapped                  addr="0x83" mapto="0x03"/><!-- STATUS -->
        <mapped                  addr="0x84" mapto="0x04"/><!-- FSR -->
        <register name="TRISA"  addr="0x85" bits="0-7" reset="11111111"/>
        <register name="TRISB"  addr="0x86" bits="0-7" reset="11111111"/>
        <mapped                  addr="0x8A" mapto="0x0A"/><!-- PCLATH -->
        <mapped                  addr="0x8B" mapto="0x0B"/><!-- INTCON -->
        <register name="PIE1"   addr="0x8C" 
                  bits="TMR1IE,TMR2IE,CCP1IE,0,TXIE,RCIE,CMIE,EEIE"/>
                  
        <register name="PCON"   addr="0x8E" reset="00001000"
                  bits="BOR,POR,0,OSCF" />
                  
        <register name="PR2"    addr="0x92" bits="" reset="11111111"/>
        <register name="TXSTA"  addr="0x98" reset="00000010" mask="11110101"
                  bits="TX9D,TRMT,BRGH,0,SYNC,TXEN,TX9,CSRC"/>
                  
        <register name="SPBRG"  addr="0x99" bits=""/>
        <register name="EEDATA" addr="0x9A" bits=""/>
        <register name="EEADR"  addr="0x9B" bits=""/>
        <register name="EECON1" addr="0x9C" bits="RD,WR,WREN,WRERR"/>
        <register name="EECON2" addr="0x9D" bits=""/>
        <register name="VRCON"  addr="0x9F" mask="11101111"
                  bits="VR0,VR1,VR2,VR3,0,VRR,VROE,VREN"/>
    </regblock>
    <datablock name="GPR1" start="0x00A0" end="0x00EF"/>
    <datablock name="RAM1" start="0x00F0" end="0x00FF" mapto="0x0070"/>
    
    <!-- BANK 2 -->
    <regblock name="SFR2" start="0x0100" end="0x010F">
        <mapped                  addr="0x100" mapto="0x00"/><!-- INDF -->
        <mapped                  addr="0x101" mapto="0x01"/><!-- TMR0 -->
        <mapped                  addr="0x102" mapto="0x02"/><!-- PCL -->
        <mapped                  addr="0x103" mapto="0x03"/><!-- STATUS -->
        <mapped                  addr="0x104" mapto="0x04"/><!-- FSR -->
        <mapped                  addr="0x106" mapto="0x06"/><!-- PORTB -->
        <mapped                  addr="0x10A" mapto="0x0A"/><!-- PCLATH -->
        <mapped                  addr="0x10B" mapto="0x0B"/><!-- INTCON -->
    </regblock>
    <datablock name="GPR2" start="0x0120" end="0x014F"/>
    <datablock name="RAM2" start="0x0170" end="0x017F"  mapto="0x0070"/>
    
    <!-- BANK 3 -->
    <regblock name="SFR3" start="0x0180" end="0x018F">
        <mapped                  addr="0x180" mapto="0x00"/><!-- INDF -->
        <mapped                  addr="0x181" mapto="0x81"/><!-- OPTION -->
        <mapped                  addr="0x182" mapto="0x02"/><!-- PCL -->
        <mapped                  addr="0x183" mapto="0x03"/><!-- STATUS -->
        <mapped                  addr="0x184" mapto="0x04"/><!-- FSR -->
        <mapped                  addr="0x186" mapto="0x86"/><!-- TRISB -->
        <mapped                  addr="0x18A" mapto="0x0A"/><!-- PCLATH -->
        <mapped                  addr="0x18B" mapto="0x0B"/><!-- INTCON -->
    </regblock>
    <datablock name="RAM3" start="0x01F0" end="0x01FF"  mapto="0x0070"/>
</parts>
